It is considered that the integration of high-speed consumer digital signal processing (DSP) application requires an efficient IC architecture which is fully adapted to the application at hand. On the other hand, the design time can be reduced substantially by maintaining only a very small cell-library and by applying powerful CAD tools. From the experience collected with a large number of realistic and practical case studies, a selection has been made of promising, efficient architectural strategies that satisfy these constraints. Guidelines for the architectural design process are proposed that depend on the required throughput and the structure of the algorithm and corresponding signal flow-graph.< >
K. KiyohashiTakuro EguchiR. TateTakeyuki Kamimoto
Hirofumi YoshidaAtsushi Hasebe