On path selection for delay fault testing considering operating conditions [logic IC testing]

Abstract

Path delays in deep submicron designs are sensitive to the operating point of the design, which is defined by the temperature and supply voltage. Moreover, a change in the operating conditions may affect different paths differently. We study a path selection technique for path delay fault test generation that takes into account possible variations in operating conditions. In developing the path selection procedure, we assume that the operating conditions are uniform across multiple gates, however, they are unknown and may assume one of a large range of values. The paths selected for test generation must include the critical paths for any operating point in this range. The study provides a quantitative analysis of path criticality at different operating conditions.