A 3-Bit GaAs Analog-to-Digital Converter

Abstract

A 3-bit GaAs analog-to-digital converter (ADC) using a parallel architecture has been designed and fabricated. A latched regenerative comparator design approach is used. Depletion mode MESFET technology was used for circuit implementation. Successful functionality tests of the comparator and the ADC have been completed on the first circuits. These show that comparator offset uniformity needs to be improved. High-speed tests will be underway shortly with results to be presented at the conference.