VLSI processor for reliable stereo matching based on window-parallel logic-in-memory architecture

Abstract

This paper presents a VLSI processor for reliable stereo matching to establish correspondence between images by selecting a desirable window size for sum of absolute differences(SAD) computation. In SAD computation, a degree of parallelism between pixels in a window changes depending on its window size, while a degree of parallelism between windows is predetermined by the input-image size. Based on this consideration, a window-parallel and pixel-serial architecture is also proposed to achieve 100% utilization of processing elements. Not only 100% utilization but also a simple interconnection network between memory modules and processing elements makes the VLSI processor much superior to the pixel-parallel-architecture-based VLSI processors.