A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Zhibin Xiao; Bevan Baas

doi:10.1007/978-3-642-45073-0_7

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A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Zhibin Xiao Bevan Baas

Year: 2013 IFIP advances in information and communication technology Pages: 125-143 Publisher: Springer Science+Business Media

DOI: 10.1007/978-3-642-45073-0_7

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Keywords:

Computer science Network topology Interconnection Topology (electrical circuits) Mesh networking Network on a chip Scalability Parallel computing Embedded system Computer network Wireless Engineering Telecommunications Electrical engineering

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Interconnection Networks and Systems

Physical Sciences → Computer Science → Computer Networks and Communications

Parallel Computing and Optimization Techniques

Physical Sciences → Computer Science → Hardware and Architecture

Embedded Systems Design Techniques

Physical Sciences → Computer Science → Hardware and Architecture

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

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