Dedicated VLSI Architectures for Adaptive Interference Suppression in Wireless Communication Systems

Abstract

In this contribution we discuss adaptive signal processing algorithms for interference suppression based on either spatial filtering using base station antenna arrays (→ "smart" antennas) or a special form of transversal filtering (→ linear equalisers for advanced DS-CDMA receivers). It is demonstrated that for reliable operation in non-stationary environments with different levels of interference, such as encountered in mobile radio, RLS-based techniques are inevitable due to their superior transient behaviour. In order to overcome the associated problems of numerical stability and large computational complexity, we propose to employ the QRD-RLS algorithm which solely relies on numerically robust transformations and can be implemented efficiently in VLSI technology based on a network of simple CORDIC arithmetic units which makes extensive use of parallel processing. The hardware implementation of such a 2D systolic array as well as an alternative pipelined linear array capable of real-time operation in high data rate systems (> 2 Mbps) is presented together with bit-true performance assessments for applications involving adaptive antennas. Special attention is given to the interactive design process required to successfully develop advanced algorithms and dedicated hardware architectures for tackling demanding signal processing tasks.