Design of a 2.7 V CMOS analog front end for CCD video systems

X. Chen; Antonio Salcedo; Roger Levinson; M.A. Soderstrand

doi:10.1109/mwscas.1997.666076

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JOURNAL ARTICLE

Design of a 2.7 V CMOS analog front end for CCD video systems

X. Chen Antonio Salcedo Roger Levinson M.A. Soderstrand

Year: 2002 Vol: 1 Pages: 233-236

DOI: 10.1109/mwscas.1997.666076

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Abstract

A 2.7 V CMOS analog front end (AFE) is integrated with a 10-bit ADC for CCD video systems. The AFE provides correlated double sampling, 6-38 dB programmable gain and consumes 20 mA under a 2.7 V supply clocked at 15 MHz. The INL and DNL of the AFE and ADC under 0.8 V input signal are 9LSB and /spl plusmn/0.5LSB.

Keywords:

CMOS Analog front-end Front and back ends Correlated double sampling Sampling (signal processing) Flash ADC Successive approximation ADC Analog signal Electronic engineering 8-bit Computer science Physics Electrical engineering Computer hardware Engineering Capacitor Voltage Digital signal processing Amplifier Comparator Detector

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CCD and CMOS Imaging Sensors

Physical Sciences → Engineering → Electrical and Electronic Engineering

Analog and Mixed-Signal Circuit Design

Physical Sciences → Engineering → Biomedical Engineering

Integrated Circuits and Semiconductor Failure Analysis

Physical Sciences → Engineering → Electrical and Electronic Engineering

Design of a 2.7 V CMOS analog front end for CCD video systems

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