In this paper, we demonstrate that high Q-factor inductors on normal 750-/spl mu/m-thick silicon substrate (in standard 0.18-/spl mu/m CMOS technology) can be achieved by optimization of the layout of the inductors. To study the effect of pattern-ground-shield (PGS) on our designed inductors, we compare the performance of the inductors with and without PGS. In addition, a state-of-the-art 4-GHz CMOS LC voltage-controlled oscillator (VCO) with phase noise of -119.94 dBc/Hz measured at 1 MHz offset frequency is reported.
Meng MiaoCuong HuynhCam Nguyen
J.-W. LeeD. H. T. VoSang Hoon HongQuoc-Hung Huynh
Siheng ZhuKun FengChao GuoJun HuHoujun SunXin Lv
Amel NeifarGhazi BouzidMohamed TrabelsiMohamed Masmoudi
Shahin Mehdizad TaleieYongping HanTino CopaniBertan BakkaloğluSayfe Kiaei