Printed circuit board routing and package layout codesign

Abstract

Given a pin-grid-array (PGA) package with an area-array of I/O pins and some devices (blocks) distributed on a printed-circuit board (PCB), an algorithm is presented in this paper to find a pin assignment solution which eases the routing in the PGA package and then improves the nets routability of the PCB. In the algorithm the routing costs of the PGA package and PCB have to be calculated separately during pin assignment. A simulated annealing technique is also applied to improve the solution by exchanging the pin assignment for some chosen nets in the PGA package. Simulation results on various PCB circuits show that PCB routings produced with pin assignment under consideration can be achieved far better than the routings without pin assignment.