Fan-Out Wafer-Level Chip-Scale Package

Shichun Qu; Yong Liu

doi:10.1007/978-1-4939-1556-9_3

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Fan-Out Wafer-Level Chip-Scale Package

Shichun Qu Yong Liu

Year: 2014 Pages: 39-62

DOI: 10.1007/978-1-4939-1556-9_3

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Keywords:

Chip-scale package Wafer Chip Scale (ratio) Wafer-scale integration Reliability engineering Computer science Embedded system Materials science Engineering Optoelectronics Telecommunications Geography Cartography

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3D IC and TSV technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Integrated Circuits and Semiconductor Failure Analysis

Physical Sciences → Engineering → Electrical and Electronic Engineering

Electronic Packaging and Soldering Technologies

Physical Sciences → Engineering → Electrical and Electronic Engineering

Fan-Out Wafer-Level Chip-Scale Package

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